As a technology of transferring data among a plurality of modules, there has been known a bus system that has been used for, for example, data transfer inside of a computer system. The bus system has been arranged so that a plurality of modules are connected through a common bus, in which the bus is used as a data transmission path among the modules in a time-divisional manner for the purpose of transferring the data. This type of bus is normally composed of address signal lines, data signal lines, a control signal lines, and clock signal lines.
As a layout of connecting the bus with the modules in the bus system, there has been known a layout of connecting each module with the bus directly or through a resistor or another layout of connecting each module with the bus in a noncontact manner with a crosstalk. The layout of connecting each module with the bus through the resistor is described in the STTL (Stub Series Terminated Logic, EIAJ ED-5512 (http://www.jeita.or.jp)). The layout of connecting each module with the bus in a noncontact manner with a crosstalk is described in JP-A-2000-132290.
Herein, FIG. 14 shows a typical arrangement of the bus system having a layout of directly connecting each module with the bus.
With reference to FIG. 14, numerals 811 and 812 denote modules to which a bus line 800 that is a data bus is connected. The modules 811 and 812 provide three-state transmitting circuits (or three-state buffers) 821 and 832 whose output terminals are connected to the bus line 800 and receiving circuits 831 and 822 whose input terminals are connected to the bus line 800, respectively.
The three-state transmitting circuits 821 and 832 are allowed to be controlled to keep each output to either one of a high-impedance state and a data output state (or level determined state). In the data output state, the output of the three-state transmitting circuits 821 and 832 is made to be any one of the state where the “L” level is outputted and the state where the “H” level is outputted according to the data value to be transferred.
In such an arrangement, in a case that the data is transferred from one module 811 to another module 812, at first, the operation is executed to make the transmitting circuits of all the modules connected to the bus line 800 be in the high-impedance state. Then, only the three-state transmitting circuit 821 of the module 811 is made to be in the data output state so that the data may be outputted to the bus line 800. Then, the data outputted onto the bus line 800 is received in the receiving circuit 822 of the module 812 and then is sent to the inside of the module 812.
In turn, FIG. 15 shows a typical arrangement of the bus system having a layout of connecting each module with the bus in a noncontact manner with a crosstalk.
With reference to FIG. 15, numerals 1011 and 1012 denote modules. The module 1011 is directly connected to a bus line 1000 served as a data bus, while the module 1012 is connected to the bus line not directly but through a directional coupler 1001. Numeral 1002 denotes a stub line for connecting the directional coupler 1001 with the module 1012. Herein, the arrangement including the bus line 1000, the coupler 1001 and the stub line 1002 is called a noncontact bus.
The modules 1011 and 1012 provide three-state transmitting circuits 1021 and 1032 and receiving circuits with hysteresis characteristic 1031 and 1022, respectively. In the module 1011, the output terminal of the three-state transmitting circuit 1021 and the input terminal of the receiving circuit with hysteresis characteristic 1031 are connected to the bus line 1000. In the module 1012, the output terminal of the transmitting circuit 1032 and the input terminal of the receiving circuit 1022 are connected to the stub line 1002.
In such an arrangement, for example, in a case that data is transferred from one module 1011 to another module 1012, at first, an operation is executed to make the transmitting circuits of all the modules connected to the bus line 100 be in a high-impedance state. Then, only the three-state transmitting circuit 1021 inside of the module 1011 is made to be in the data output state so that the data may be outputted onto the bus line 1000. The data outputted onto the bus line 1000 is transformed into a differential pulse caused by a crosstalk in the directional coupler 1001. This differential pulse is received in the receiving circuit with hysteresis characteristic 1022 inside of the module 1012 through the stub wire 1002. Then, the hysteresis characteristic of the receiving circuit 1022 causes this differential signal to be decoded into the same signal as the output signal of the transmitting circuit 1021. The decoded signal is sent into the inside of the module 1012.
The aforementioned bus system has difficulty in speeding up a data transfer cycle (bus period).
At first, FIG. 16 shows a timing chart appearing in the case of consecutively transferring four pieces of data from the module 811 to the module 812 in the bus system (that has a layout of directly connecting each module with the bus) shown in FIG. 14.
In this case, as shown in FIG. 16(a), on the bus line 800, a transition time tr1 from the high impedance state where no data is outputted to the determination of the first data piece is made longer that the transition time tr2 from the output end of the one previous data piece to the termination of each data later than the first data piece. This is because in the three-state transmitting circuit 821 of the module 811 the waveform appearing in the transition from the high impedance state to the data output state is duller than the waveform appearing in the transition from the “L” level output state to the “H” level output state or the “H” level output state to the “L” level output state.
As shown in FIG. 16(b), as to the delay time from the time when the receiving circuit 822 of the module 812 receives the switching signal of the data to the determination of the output data of the receiving circuit 822, the delay time td1 for the first data piece is made longer than the delay time td2 for the second or later data piece. This is because a difference takes place between the delay times tr1 and tr2 and the delay time is characterized to be longer as the waveform transition time of the input signal of the receiving circuit 822 is made longer as shown in FIG. 17.
As set forth above, in the bus system having a layout of directly connecting each module with the bus, the pulse width tw1 of the first data piece to be outputted to the inside of the module by the receiving circuit of the module itself is made shorter than the pulse width tw2 of the second or later data piece. This phenomenon becomes an obstacle to speeding up the data transfer cycle (bus period).
Next, FIG. 18 shows a timing chart appearing in the case of consecutively transferring four data pieces from the module 1011 to the module 1012 in the bus system shown in FIG. 15 (that has a layout of connecting each module with the bus not directly but with a crosstalk).
In this case, as shown in FIG. 18(b), the differential pulse 1101 for the first data piece, received by the receiving circuit with hysteresis characteristic 1022, is made about half as long as the differential pulse 1102 for the second or later data piece.
This is because as to the second or later data piece the differential pulse is caused according to a relatively great change from the “L” level to the “H” level or “H” level to the “L” level, while as to the first data piece the differential pulse is caused according to the relatively small change from the middle level of the “H” level and the “L” level to the “H” level or the “L” level. Before the first data piece, that is, in the state that no module outputs the data, the level of the bus line 1000 is normally made to be the middle level between the “H” level and the “L” level through the use of the termination resistor.
As described above, in the bus system that has a layout of connecting each module with the bus not directly but with the crosstalk, the differential pulse for the first data piece is made smaller than the differential pulse for the second or later data piece. In order to properly receive the differential pulse for the first data piece, the sensitivity of the receiving circuit with hysteresis characteristic may be enhanced. However, the enhanced sensitivity leads to disability of securing a sufficient noise margin for the noise caused in speeding up the data transfer cycle (bus period). This disability becomes an obstacle to speeding up the data transfer cycle (bus period).